As opposed to planar complementary metal oxide semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source and drain and a top source and drain disposed on the fin channel. VFETs are being explored as a viable device option for continued CMOS scaling beyond the 7 nanometer (nm) technology node.
Once the gate has been formed on the vertical fin channel, a notable challenge associated with the VFET design is to be able to then form the source and drain on top of the channel without undesirably creating a short to the gate. Specifically, in order to form the top source/drain, the top of the vertical fin channel has to be exposed. During this process, the gate surrounding the vertical fin channel can also inadvertently become exposed. Thus, when the top source and drain epitaxy is grown on the top of the vertical fin channel, parasitic growth can also occur on the exposed gate merging with the top source and drain and shorting the top source and drain to the gate.
Thus, improved techniques for fabricating a VFET device whereby the gate is protected during the top source and drain epitaxy would be desirable.